1. Field of the Invention
The present invention relates to a sampling circuit for an analog signal and an image display device using the sampling circuit.
2. Description of the Related Art
Conventionally, sampling circuits for an analog signal have been utilized in various fields, and their circuits have been specifically designed for the different fields. Hereinbelow, circuitry for a data line drive circuit of a liquid crystal display device used as an image display device are specifically described. Naturally, these circuits are applicable, not only to liquid crystal display devices, but also to other fields.
A liquid crystal display device of an active matrix drive method is conventionally known. As shown in FIG. 11A, such an active matrix liquid crystal display device includes an array of pixels PIX, a scan signal line drive circuit GD, and a data signal line drive circuit SD. A number of scan signal lines GL and a number of data signal lines SL run perpendicular to each other across the pixel array. Pixels PIX are formed in a matrix, each being defined by two adjacent scan signal lines GL and two adjacent data signal lines SL. The data signal line drive circuit SD samples a video signal DAT input thereinto in synchronization with a timing signal such as a clock signal CKS and, after amplifying as required, writes the sampled video signal in the data signal lines SL. The scan signal line drive circuit GD sequentially selects the scan signal lines GL in synchronization with a timing signal such as a clock signal CKG, so as to control the open/close of a switching element of each pixel PIX, thus allowing the video signal (data) written in each data signal line SL to be supplied to a pixel electrode of each pixel PIX or data already written in each pixel PIX to be retained.
As shown in FIG. 11B, each pixel PIX includes a field effect transistor SW as the switching element and a pixel capacitance (composed of a liquid crystal capacitance C.sub.L and, as required, a storage capacitance C.sub.S). A data signal line SL.sub.i is connected to one electrode of the pixel capacitance via a drain and a source of the transistor SW. A scan signal line GL.sub.j is connected to a gate of the transistor SW. The other electrode of the pixel capacitance is connected to a common electrode line shared by all pixels. The transmittance or reflectance of the liquid crystal layer is modulated with a display voltage applied to the liquid crystal capacitance C.sub.L of each pixel capacitance, thus realizing image display.
In conventional active matrix liquid crystal display devices, an amorphous silicon thin film formed on a transparent substrate is used as a semiconductor layer of each transistor SW, and the scan signal line drive circuit GD and the data signal line drive circuit SD are formed as individual external ICs.
In recent years, however, in response to the requests for increase in the drive power of transistors for pixel display, reduction in the cost for mounting driver ICs, improvement in the reliability at the mounting, and the like which have arisen with the recent trend of enlarging the display screen size, techniques for monolithically forming a pixel array and drive circuits on a substrate using a polysilicon thin film have been reported. Furthermore, for further enlarging the display screen size and reducing the cost, there have been attempts to form these elements using a polysilicon thin film on a glass substrate at a process temperature below a glass strain point (about 600.degree. C.). Such polysilicon thin film transistors (TFTs), however, have inferior device characteristics compared with transistors formed on a single crystalline silicon substrate. For example, the polysilicon TFTs have a large size and a small carrier mobility. In other words, in order to obtain drive power of the same magnitude, polysilicon TFTs with a larger size (channel width) are required, compared with the case of using single crystalline silicon.
Hereinbelow, how image data is written to the data signal lines will be described. The data signal lines are driven by two methods: a point-at-a-time drive method and a line-at-a-time drive method.
First, the point-at-a-time drive method will be described with reference to FIG. 6. A video signal input into a video signal line DAT is written to the data signal lines SL depending on the open/closed state of corresponding sampling switches SWT conducted in synchronization with an output pulse from corresponding stage shift registers SR as scan circuits which receive the clock signal CKS and a start signal SPS. In this procedure, each buffer circuit LAT receives the signal from the corresponding shift register SR, retains and amplifies the signal, and produces an inverted signal as required. In this method, the period available for writing the video signal in each data signal line SL is only 1/(total number of data signal lines) of an effective horizontal scan period (about 80% of a horizontal scan period). Accordingly, the signal may not be sufficiently written in the data signal line when the time constant (product of capacitance and resistance) of the data signal line increases with the enlargement of the display screen size and/or when the sampling time is shortened with the improvement in precision. This degrades display quality. This is particularly true when the sampling switches SWT are composed of transistors with a small drive power such as the polysilicon TFTs as described above. To overcome this problem, conventionally, the channel width of the transistor constituting the sampling switch SWT is made large to ensure sufficient write performance.
The line-at-a-time drive method will be described with reference to FIG. 7.
A video signal is sampled via sampling switches SWT1 and temporarily stored in sampling capacitors Csmp. When a transfer signal transmitted through a transfer signal line TRF activates transfer switches SWT2, the charges stored in the sampling capacitors are output as data signals to the data signal lines SL via corresponding signal amplifiers AMP during the next horizontal scan period. In general, the sampling capacitor Csmp is smaller than the data signal line SL in capacitance. Accordingly, the above-described problem which occurs in the point-at-a-time drive method is not so significant. However, insufficient writing as in the point-at-a-time drive method may occur if the capacitance of each sampling capacitor Csmp is increased to compensate for a temporal decrease in the amount of charge retained in the sampling capacitor Csmp due to a leak current flowing through the sampling switch SWT1 and a reduction in the amount of charge due to capacitance division at the signal transfer to the signal amplifier AMP. This is especially true as the precision of the display becomes higher. In such a case, also, the channel width of the transistor constituting the sampling switch SWT1 is made large to ensure sufficient write performance. In FIG. 7, the reference code Ch denotes a holding capacitor.
FIG. 12 shows a configuration of a conventional sampling circuit. Referring to FIG. 12, the sampling switch SWT is a complementary metal oxide semiconductor (CMOS) composed of an n-channel transistor NM and a p-channel transistor PM as sampling transistors connected in parallel. In this configuration, the positive level of a video signal is written to the data signal line SL via the n-channel transistor NM, while the negative level of the video signal is written to the data signal line SL via the p-channel transistor PM. A timing signal generated by the shift register SR is supplied to a gate of the n-channel transistor NM or the p-channel transistor PM via a plurality of inverting circuits INV1 to INV4 and some logic circuits (not shown) disposed as required. The inverting circuits INV1 to INV4 are disposed so as to drive the sampling transistors having a large channel width (large input load) with the timing signal from the shift register SR having a small drive power, and to match the phase (polarity) of the timing signal. The inverting circuit at a later stage is composed of a transistor with a larger channel width. The logic circuits allow the video signal to be sampled only in a required minimum amount, and to control the timing of the sampling. Since signals of the reverse phases need to be input into the gates of the n-channel transistor NM and the p-channel transistor PM, an odd number of (normally, one) circuits are additionally disposed on the route to one of the sampling transistors to produce the signals with the reverse phases.
In the above conventional CMOS sampling circuit, the channel length and width of the n-channel transistor NM are substantially the same as those of the p-channel transistor PM as shown in FIG. 12. This configuration is shown, for example, in FIG. 13 (page 61) of "Driver Circuits for AMLCDs", 1994, International Display Research Conference, pp. 56-64.
In the conventional configuration shown in the above figure, however, the write period differs depending on polarity of the video signal. This is mainly because the carrier mobility of the n-channel transistor NM is different from that of the p-channel transistor PM. It is generally known that the carrier mobility of the p-channel transistor PM is smaller than that of the n-channel transistor NM.
In the above case, especially if a sufficient allowance of time is not available for the writing, the positive level of a data signal is different from the negative level thereof. This is likely to cause flickering in a device employing a polarity inversion drive method such as liquid crystal display devices.
In order to avoid this problem, the drive power of the n-channel transistor NM and the p-channel transistor PM should be the same. The simplest way to accomplish this is to set the channel widths W of the sampling transistors in inverse proportion to their carrier nobilities .mu.. In other words, the value of .mu..times.W for the n-channel transistor NM should be the same as that for the p-channel transistor PM. For example, if the carrier mobility of the n-channel transistor NM is twice that of the p-channel transistor PM, the channel width of the n-channel transistor NM should be a half that of the p-channel transistor PM, as shown in FIG. 13. This is possible because, in general, the n-channel transistor NM and the p-channel transistor PM are substantially the same in the channel length, the thickness of the gate insulating film, and the like.
The above solution, however, causes a new problem. That is, as shown in FIGS. 14A and 14B, when the transistor is turned from the ON state to the OFF state, the charge stored in a channel capacitance of the transistor (capacitance between the gate electrode and a channel region) is divided and flows to the source side and the drain side. When the drain side includes a floating node having a predetermined capacitance such as the data signal line, the potential of the floating node fluctuates with the divided charge. Further, the amount of charge stored in the channel capacitance is proportional to the area of the channel region. Accordingly, when the channel width differs between the two sampling transistors as described above, the influence of the potential fluctuation at the data signal line also differs. This refers to the case where the channel lengths of the two transistors are the same.
In the above case, the potential fluctuation at the data signal line occurring when the transistor is turned off is asymmetric between when the sampled signal is positive and when the sampled signal is negative. This is also likely to cause flickering in a device of the polarity inversion drive method such as liquid crystal display devices.
In a data signal line drive circuit having a plurality of sampling circuits, it is possible to eliminate the influence of the potential fluctuation at the data signal line on the image display, as far as the influence is fixed, by adjusting the level of the video signal. However, if the threshold voltage and the like vary among the plurality of sampling circuits, the potential fluctuation at the data signal line varies, resulting in degradation of the display image (vertical stripes, etc.).
In particular, the sampling circuit composed of polysilicon TFTs tends to be largely influenced by the potential fluctuation because a larger channel width is required as described above. Therefore, it is important to reduce the channel area as much as possible.